Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device that may decrease parasitic capacitance between bit lines and storage node contact plugs and a method for fabricating the semiconductor device.
In a semiconductor device such as a Dynamic Random Access Memory (DRAM) device, a capacitor and a bit line perform an electrical operation through a source/drain contact. As semiconductor devices shrink, storage node contact plugs (SNC) and bit lines (or bit line contacts) have to be formed within a small area. In this case, the storage node contact plugs and the bit lines are laid adjacent to each other with a thin spacer between them. The spacer is typically a nitride layer, such as a silicon nitride layer.
Generally, a silicon nitride layer has a high dielectric rate and thus it is not effective in suppressing the parasitic capacitance (Cb) between bit lines and storage node contact plugs.
Therefore, the parasitic capacitance between bit lines and storage node contact plugs may increase, and an increase in the parasitic capacitance decreases a sensing margin.